This invention relates generally to automatic bias circuits and more specifically to baseline wander compensation circuits for alternating current (AC) coupled signal limiters for synchronous baseband data detectors. Radio data communication systems, in particular, may make use of the present invention to further compensate direct current (DC) offset voltages which result from differences in the frequencies of transmission and reception.
Portable and mobile radio transceivers are commonly used for communications of data messages. These data transceivers can be found in paging systems and two-way communications systems such as those used by the public and government agencies. Recently, portable radio transceivers have found use in portable data terminals which may be used to communicate with a host computer via radio or wireline.
Most devices which are used for radio data communications are operated in a synchronous mode. That is, the local clock signal used to operate the radio data terminal data decoding is phase compensated so that the transitions of the local clock signal are aligned with the transitions of the incoming data signal.
Several well known techniques have been developed for synchronizing a local clock to a received data signal. One common technique advances or retards the local clock signal by adding pulses from a signal coupled to a frequency divider chain which provides a local signal. Another technique for clock recovery utilizes a programmable divider coupled to a reference clock signal. The recovered clock signal is compared to the received data signal and the divider is programmably altered to shift the phase of the recovered clock. This latter technique for phase adjustments is described in U.S. Pat. No. 4,400,817 assigned to the assignee of the present invention.
To avoid the relatively large amount of time to acquire a clock signal in the presence of data bias distortion and phase ambiguities occuring in the limiter and discriminator stages of a frequency modulation receiver commonly used in the aforementioned applications, an automatic clock recovery circuit was invented and disclosed in U.S. patent application No. 564,975, now U.S. Pat. No. 4,575,863, filed in behalf of Butcher on Dec. 22, 1983 and assigned to the assignee of the present invention. The automatic clock recovery circuit disclosed therein advances or retards the phase of a recovered clock signal depending upon the relative phase of the received data signal and recovered clock signal. It also disables the retard correction immediately following advance correction and disables the advance correction based on certain phase conditions between the received data signal and the recovered clock signal.
To process and detect the received data signal, the signal is coupled to a data signal limiter circuit, which regenerates squared-up waveforms with steep rising and falling edges to provide binary "1" and "0" information to a data decoder. However, a difference in the operational frequencies of the receiver and transmitter in a radio system causes an offset DC voltage to be superimposed on the received signal. Additionally, AC coupling of the received signal may result in an offset voltage being added to the received signal, particularly when the signal consists of a long consecutive string of digital "1's" or "0's". These aforementioned offsets, which may change over time, constitute a wander of the data baseline and complicate the detection and decoding process.
Solutions to this wander have generally included peak-to-peak detection of the data signal and subsequent generation of a baseline signal equal to 1/2 the detected peak-to-peak voltage such as described in U.S. Pat. Nos. 3,846,710 and 4,175,256 assigned to the assignee of the present invention. In those data systems employing synchronous data decoding, the data signal peak-to-peak average detection may operate too slowly to establish a baseline to enable detection of a synchronizing signal.
The invention disclosed in U.S. patent application No. 564,974, now U.S. Pat. No. 4,575,863, filed in behalf of Butcher, et al., on Dec. 22, 1983 and assigned to the assignee of the present invention, addresses the timing problem of synchronization detection by incorporating a dual time constant bias recovery circuit into the transceiver. A short time constant is used during the period when a data message synchronization is being received and is programmably switched to a long time constant for the duration of the synchronized data message. However, since the dual time constant recovery circuit follows the average DC component of the data signal, long unbalanced data messages with AC coupling may result in improper baseline determination.